This invention pertains generally to overcurrent relay circuits and pertains particularly to timing circuits for overcurrent relay circuitry to be used with a small signal input, e.g. in the millivolt range.
The purpose of an overcurrent relay circuit is to trip an interrupter when the current in a circuit to be protected rises to levels potentially dangerous to the components in the circuit. In order to ensure that interruption does not occur accidentally, but only when an overcurrent condition arises and persists long enough to expose the circuitry to damage, it is common to provide such relay circuitry with a time delay, so that the protected circuit is interrupted only if the overcurrent condition persists a certain minimum time. The required overcurrent duration varies inversely with the severity of the overcurrent condition. Examples are to be found in U.S. Pat. No. 3,319,127, to Zocholl et al., and U.S. Pat. No. 3,327,171, to Lipnitz et al., both assigned to the assignee of the present application. One means of using a multinode R-C circuit to produce the required time delay is disclosed in applicant's copending application Ser. No. 949,015, filed Oct. 6, 1978, entitled SOLID STATE RELAY, and assigned to the assignee of the present application, now U.S. Pat. No. 4,259,706. The disclosure of the cited copending application is incorporated herein by reference.
Timing circuits designed to provide the necessary time delay, as exemplified by the cited patents and copending application, contain a number of capacitors whose values are related to each other in a manner dictated by the mathematical relation it is desired should exist between the severity of the overcurrent condition and the length of the time delay before interruption. In order for the timing circuits to emulate the chosen relation accurately, capacitors having precisely the correct values must be used. This generally requires the use of non-standard values of capacitance, which greatly increases the cost of such circuitry.